Regviz

Silicon Labs /EFR32MG24A120F1536GM48 /MODEM_NS /SISTATUS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SISTATUS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MODEM_S/SISTATUS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SISTATE0 (NOISE)NOISE 0LWPEAKCOUNT 0NARROWCOUNT 0 (TIMELOCK)TIMELOCK 0 (SUPERCHIPFAIL)SUPERCHIPFAIL 0 (SUPERCHIPPASS)SUPERCHIPPASS 0TIMEOFFSET 0CORRPASSNUM0 (SNIFFDONE)SNIFFDONE 0 (SIDET)SIDET

Description

No Description

Fields

SISTATE

SI main FSM
NOISE

Noisy short window
LWPEAKCOUNT

Peak count
NARROWCOUNT

Narrow pulse count
TIMELOCK

Timing locked
SUPERCHIPFAIL

Superchip fail
SUPERCHIPPASS

Superchip pass
TIMEOFFSET

Timing offset
CORRPASSNUM

CORR success num
SNIFFDONE

Sniff done
SIDET

Signal detected

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data